The present invention relates to semiconductor devices, which use nitride semiconductors and are applicable to high-power transistors for use in power supply circuits in consumer appliances, and methods for fabricating those semiconductor devices.
The Group III nitride semiconductors, typified by gallium nitride (GaN), have high breakdown electric field; the band gaps of gallium nitride (GaN) and aluminum nitride (AlN) are as high as 3.4 eV and 6.2 eV, respectively, at room temperature. In addition, the Group III nitride semiconductors have the advantage that electron saturation drift velocity is higher as compared with compound semiconductors, such as gallium arsenide, and semiconductors made of silicon (Si). The Group III nitride semiconductors are thus under vigorous research and development for application to high-voltage high-power switching elements.
Furthermore, it has been reported that two-dimensional electron gas having a sheet carrier concentration of 1×1013 cm−2 or higher is generated at the heterointerface in a heterostructure of AlGaN and GaN, in which the plane orientation of the interface is (0001), by spontaneous polarization and piezo polarization occurring perpendicularly with respect to the interface even when the heterostructure is not doped, and that a so-called normally-on heterojunction field effect transistor having low on-resistance can be formed by utilizing that two-dimensional electron gas (see, for example, p 803 in IEDM Tech. Digest 2004 by M. Hikita et al.). In order to increase the breakdown voltage of such a planar transistor, the distance between the gate electrode and the drain electrode must be increased. For example, in the above-described GaN-based transistor, a breakdown voltage of 350 V is achieved by increasing the distance between the gate electrode and the drain electrode to about 10 μm.
To reduce the electric field in the end portion of the gate electrode for further increase in breakdown voltage, it is also effective to employ a field plate structure, in which a source electrode is provided above a passivation film, and the like.
However, in realizing a high-voltage device by such a conventional planar transistor, there are problems in that the chip size is increased and the fabrication process becomes complicated.
On the other hand, as a device structure that enables higher breakdown voltage with smaller chip area, there are transistors having a vertical structure, called a PBT (permeable base transistor) or an SIT (static induction transistor). Such vertical transistors typically have a structure, in which a projection is formed on a semiconductor layer with a source electrode and a drain electrode formed on the top and back sides of the projection, a gate electrode is then formed on the side faces of the projection, and the channel current is controlled by gate voltage applied to the gate electrode. For an example in which this vertical transistor structure was applied to nitride semiconductors, suggestions of structure and device simulation results have been reported (see, for example, V. Camarchia et al. IEEE Electron Device Letters 23 (2002)303).
The device structure described in the second literature is as follows.
A first n+-type GaN layer is formed on a drain electrode, and an n−-type GaN layer having a projection and a second n+-type GaN layer are formed over the first n+-type GaN layer. A gate electrode is formed in the lower portion and on the side faces of the projection so as to be in contact with the n−-type GaN layer, while a source electrode is formed on the top surface of the projection. Current passing across the source and drain electrodes can be controlled by application of negative voltage to the gate electrode, thereby allowing realization of a field effect transistor. In this vertical device, the drain breakdown voltage can be increased by increasing the thickness of the part of the n−-type GaN layer located under the gate electrode and by lowering the carrier concentration in the n−-type GaN layer, whereby high breakdown voltage can be achieved with the chip area kept small.
Nevertheless, for the nitride semiconductor field effect transistor having the conventional vertical structure, the second literature does not describe a specific method for forming the gate electrode in such a manner that the gate electrode is in contact with the side faces of the projection, and it is very difficult to actually form the gate electrode on the side faces of the projection.
A possible conventional fabrication method is to selectively form the gate electrode to the side of the projection by using a mask pattern, after the source electrode is formed, for example. However, with consideration given also to the mask alignment accuracy, the gate electrode can only be formed about 0.2 μm away from the side faces, for example, such that the drain electrode cannot be sufficiently controlled by the gate voltage. Therefore, excellent pinch-off operation cannot be realized, and it also becomes difficult to achieve normally-on operation that is strongly required for a high-voltage power element.
As described above, there is a problem in that it is difficult to realize a practical vertical nitride semiconductor device having small chip area.
In view of the above problem, it is therefore an object of the present invention to realize a semiconductor device made of nitride semiconductors and having small chip area and excellent device characteristics.